Comparative Evaluation of Three Phase Three Level Neutral Point Clamped Z-Source Inverters using Advanced PWM Control Strategies

Three-level Z-source inverters are recent single-stage topological solutions proposed for buck-boost energy conversion with all favorable advantages of three-level switching retained. Despite their effectiveness in achieving voltage buck-boost conversion, existing three-level Z-source inverters use two impedance networks and two isolated dc sources, which can significantly increase the overall system cost and require a more complex modulator for balancing the network inductive voltage boosting. Offering a number of less costly alternatives, this paper presents the design and control of two threelevel Z-source inverters, whose output voltage can be stepped down or up using only a single impedance network connected between the dc input source and either a neutral-point-clamped (NPC) or dc-link cascaded inverter circuitry. This paper investigates the carrier based modulation schemes (SPWM and Modified SVPWM) of three-level three phase Z-source inverters with either two Z-source networks or single Z-source network connected between the dc sources and inverter circuitry. With the proper offset added for achieving both optimized harmonic performance and fundamental output voltage, the proposed modulation schemes of three-level Z-source inverters can satisfy the expected boost operation under unbalanced modulation conditions. The Simulation has been performed through Matlab/Simulink and relative simulation results with conventional method have been presented to validate the proposed method. 240 K. Sreekanth et al Index Terms — Neutral-point clamped (NPC) Z-source inverters, PWM Schemes, THD. INTRODUCTION The Z-impedance network consists of L and C components connected in an X fashion. The firing control of the Z-source inverter includes the shoot through states. The Zsource inverter advantageously utilizes the shoot-through state to boost the DC bus voltage by gating on both the upper and lower switches of a phase leg. Three-level neutral-point-clamped (NPC) inverters, having many inherent advantages, are commonly used as the preferred topology for medium voltage ac drives [1], and have recently been explored for other low-voltage applications including grid-interfacing power converters and high-speed drive converters [2], [3]. Despite their generally favorable output performance, NPC inverters are constrained by their ability to perform only voltage-buck operation with buck-boost energy conversion, usually achieved by connecting various dc-dc boost converters to the front ends of the dc-ac inverters. These two-stage solutions are usually more costly and can be harder to control, since they involve more active and passive components. Offering a singlestage solution, [4], [5] propose the buck-boost Z-source NPC inverter, whose topology is illustrated in Fig. 1 (can be viewed as an extension from the two-level Zsource inverter proposed in [6]). Compared to the traditional NPC inverter, the inverter in Fig. 1 uses two additional Z-source impedance networks for boosting its dc input voltage from Vdc to a higher dc link voltage for driving the inverter directly. Although theoretically feasible, the inverter in Fig. 1 is not a favorable economical solution, since it uses two isolated dc sources and a number of passive elements, which can significantly increase the cost, size and weight of the inverter. Fig.1 Topology of Z-source NPC inverter with two LC impedance networks. With the above-described disadvantages in view and aiming to offer better alternatives, this letter presents the design of a Z-source NPC inverter that use only half the passive elements. With the integration of an appropriate pulse-width Comparative Evaluation of Three Phase Three Level Neutral Point 241 modulation (PWM) scheme, the proposed inverters can operate with the correct voltsec average and inductive voltage boosting produced at all instances, while using only the minimum of six device commutations per switching cycle for continuous PWM switching. Therefore, compared to the dual Z-source NPC inverter presented in [4], [5], the single Z-source inverters proposed in this letter have equally good Performance with only a slight degradation in high-frequency switching (not fundamental) performance expected. This is more than compensated by the reduced element count and lower system cost achieved by the inverters. Implementation wise, the inverters can be controlled using a generic alternative phase opposition disposition (APOD) carrier-based modulator with an appropriate triplen offset and time advance/delay added. OPERATIONAL PRINCIPLES OF SINGLE ZSOURCE THREELEVEL INVERTERS Fig. 2 shows the topologies of the proposed Zsource NPC and DCLC inverters, where a single Z-source impedance network, consisting of a split inductor (L1 and L2) and two capacitors (C1 and C2) are connected between the input split-dc source (can be implemented using a single dc source and two series-connected capacitors) and inverter circuitry. Compared to the inverter topology shown in Fig. 1, the proposed Zsource inverters clearly have the advantage of using only half the passive components and only a single split-dc source, which can either be isolated or non-isolated. Although the system cost is not expected to drop by half, since the voltage rating of the dc capacitors needed by the proposed inverter is nearly double that of the inverter shown in Fig. 1 (current rating of the inductors remains unchanged), the saving is still expected to be relatively sizable. This is because the proposed inverters use only a single split-dc source, implying that isolation transformers and additional rectifier circuits needed by the inverter in Fig. 1 (if isolated dc power supplies are not readily available) are omitted. Fig.2: Topology of Z-source NPC inverter using only a single LC impedance networks. 242 K. Sreekanth et al Under voltage-buck operation, the Z-source inverters are controlled with their ac outputs transiting between the three distinct voltage levels of 0 V and using the phaseleg switching states shown in Table I, which in principle are similar to those assumed by a traditional three-level inverter. Alternatively, when voltage-boost operation is commanded, both inverters must function with an additional shoot-through state inserted. A visibly obvious method for introducing the shoot-through state is to turn ON all switches from the same phase-leg simultaneously (e.g., {SA1, SA1, SA2, SA2} in Fig.2) to give the simplified circuit representation shown in Fig. 3(a) with input diodes D1 and D2 open-circuited. (Note that the turning ON of all switches from a phase leg to effect a short circuit is not the “minimal-loss” method, as explained in Section III, where a better shoot-through technique is also presented.) It is inferred that the presented Z-source inverters do not need dead-time delay for shortcircuit protection, unlike most traditional inverters. Thus, the presented Z-source inverters are expected to perform better, since performance limitations commonly associated with dead-time delay are avoided. Fig. 3. Simplified representations of single Z-source inverters when in (a) shootthrough and (b) non-shoot-through states. Table 1. Switching states of Three level Z-Source NPC State Type ON Switches ON Diodes Non Shoot-through SA1,SA2 D1,D2 + 2 Non Shoot-through SA2, 1 D1,D2 DA1orDA2 0 NonShootthrough 1, 2 D1,D2 − 2 Comparative Evaluation of Three Phase Three Level Neutral Point 243 Shootthrough (not preferred) SA1,SA2, 1, 2 . . . .. . 0 Shoot-through (preferred) SA1,SA2, 1, SB2, 1 , 2 DA2,DB1 0 Using the simplified circuit shown in Fig. 3(a) and assuming that VL1 = VL2 = VL and VC1 = VC2 = VC for a symmetrical network, the capacitive and inductive voltages of the single Z-source impedance network can be expressed as (1) during the shootthrough duration T0. VL = VC ------------(1) Upon reverting to a non-shoot-through state during interval T1, the inverters resume the circuit representation shown in Fig. 3(b), where the inverter circuitry and external load are represented by a simplified current source. Using this circuit representation, the capacitive and inductive voltages are re-expressed as VL = 2Vdc – VC Averaging VL over a switching cycle T then gives VC = 2 Vdc (1-T0/T)/(1-2 T0/T) -----(2) Using (2), the inverter dc-link voltage Vi and peak ac output voltage Vx ( x =A,B or C ) when in a non-shoot-through state are derived as Vi = VC VL = 2 VC – 2 Vdc = 2 Vdc/(1-2 T0/T) Vx = M Vi /2 = M B Vdc where M is modulation index and B is is the boost factor (B = 1/(1-2 T0/T)) , which should be set to unity for voltage-buck operation and B > 1 for voltage-boost operation. MODULATION SCHEME FOR TWO LEVEL ZSI Being different from the balanced three-phase operation, the carrier-based references have to be generated using appropriate offset plus the primarily derived sine waves. For optimizing the harmonic performance, the expected offset in sine-triangle modulation has been induced in [11] which would be summarized here briefly to demonstrate the three phase operation clearly. The offset for two-level optimal switching can be mathematically expressed as: V = −V 2 ⁄ , V > 0 −V 2 ⁄ , V < 0 −(V + V ) 2 ⁄ , V > 0 V < 0 Where, Vmax = max(Va, Vb Vc) and Vmin = min(Va, Vb Vc). The offset for multilevel optimal switching therefore can be further derived from 244 K. Sreekanth et al